1. Technical Field
This invention generally relates to semiconductor devices, and more specifically relates to self-test devices for memory arrays.
2. Background Art
The proliferation of modem electronics is due in large part to the development of the integrated circuit. An application specific integrated circuit (ASIC) is a collection of logic and memory circuits designed to perform a specific task to meet the needs of a customer application. ASIC designs are implemented on a silicon die by mapping logic functions to a set of pre-designed, pre-verified logic circuits. These circuits range from the simplest functions to highly complex circuits referred to as “cores.” Cores are typically high level industry-standard functions, such as a digital signal processor (DSP), an advanced RISC machines (ARM) microprocessor, an Ethernet function, or a peripheral component interconnect (PCI) controller. With a particular design in mind, customers can quickly assemble an ASIC design by using cores as building blocks.
One of the more commonly used cores are those that provide memory arrays for use in ASIC. Typically, memory cores are designed to be compilable, i.e., the parameters of the memory array can be customized to meet the requirements of a particular design. Typically, a compilable memory core allows the design to specify parameters such as the number or words and the width of the words. Additionally, compilable memory array cores typically allow designers to specify decode options and other parameters. Thus, one ASIC memory array core can provide memory structures for a wide variety of applications.
Modern memory arrays commonly include self-test circuitry designed to facilitate testing of the memory array after fabrication. These devices, typically referred to as “built-in-self-test” (BIST) controllers, provide the memory core with the ability to perform self tests to determine which cells in the memory are functioning properly. Typically, these BIST controllers provide the ability to perform a test pattern routing that involves writing to each memory cell in the array, and then reading from the cells to determine which cells are operating properly. In particular, the BIST controller writes a defined pattern into the memory, and reads the data back from the array. The read data is then compared to the “expect data” by the memory array, and the RAM sends back a pass/fail signal. The BIST then logs the pass fail, and uses that information to determine whether the memories embedded within the ASIC are functional.
The use of traditional BIST controllers in ASIC design has significant limitations. First, it has been traditionally difficult to adapt BIST controllers to compilable memory arrays. In particular, it has been difficult to design “compilable” BIST controllers that were able to efficiently test memory arrays that could be compiled to different sizes. Typically, BIST controller designs that were “compilable” to work with different sizes of memory arrays have been excessively difficult, and introduced significant complexity to the design and fabrication of the ASIC.
Another difficulty faced in prior art solutions is the inability of prior art BIST controllers to test multiple memory arrays on an ASIC where the memory arrays are of different sizes. For example, if an ASIC design required two different memory arrays, each having a different number of words or different decode options, the ASIC would typically require two different BIST controllers. This was a direct result of the specialization needed by BIST controllers to accurately test memory arrays of a particular size. For example, a BIST controller compiled to test a memory array having 1 k words (i.e., a 1 k×16 array) could not test an array having 2 k words, (i.e., a 2 k×16 array). Additionally, a BIST controller compiled to test a memory array with a 4:1 decode option would not be able to test a memory array compiled with an 8:1 decode option.
The reason for this limitation is that test errors would occur when the BIST controller attempts to test addresses outside of the actual dimensions of the memory array. In particular, if the BIST controller attempts to write to a memory address that does not exist, it would likely instead write to another, unknown location in the array, and thus corrupting the data in the memory array. In addition, when the BIST controller attempts to read from a memory address that does not exist, it is likely that it would instead read a random address in the array, making it again impossible to do a valid compare.
To overcome this, prior art solutions have required multiple BIST controllers, with a different BIST controller for each size memory array in the ASIC. Again, this solution is not desirable because of the excessive chip area used in the ASIC by having multiple BIST controllers.
Thus, what is needed is a method and apparatus that provides for increased BIST flexibility without the complexity of a compilable BIST circuit. Additionally, what is needed is the ability to use a single BIST to test multiple memory arrays of different sizes.